Reading data from a memory may be accomplished in a variety of ways. One possible way, used particularly in flash memories, is burst memory access. Burst memory access involves reading either a fixed number of bytes (words) (for example, 4 or 8) from memory or, alternatively, reading a continuous stream of bytes in sequence without interruption beginning from a starting address. The reading of the burst data is very fast because the data has been previously fetched from the memory and put into a buffer.
The concept of burst memory access is based on the assumption that a microprocessor, or other user, will very likely need additional bytes at addresses following a starting address after reading the first byte at the starting address. Thus, when the user requests data from a starting address, a memory in burst mode will fill its buffer with some additional data from other addresses according to a predefined burst mode address sequence or pattern (which may be ascending, descending, aligned or linear, for example) and according to a burst address space size, without waiting to be asked for the next byte. The memory then applies the burst address to a memory array to access data at each burst address location. This additional data will then be immediately available to the user without needing to fetch each word from memory. Burst reading is widely used in many memory architectures, as opposed to other types of synchronous accesses, because it is fast and consumes less power.
Increasingly, in memory applications, burst data may come from two or more channels, each containing different types of information. For example, one channel may be an MP3 data stream (Or other popular audio compression format) from a first starting address, and a second channel may be code to be executed by a microprocessor from a second starting address. Since generally there is only one system bus, and one mechanism for burst mode filling of a memory buffer, it is necessary to switch from one channel to the other and delays inevitably result.
The delays result because new burst data is not available immediately when the request for new data from a new starting address is made. When the starting address changes, the memory needs time to fetch new data and load it into the memory buffer. This time is called “latency” and is normally expressed in terms of a number of synchronous clock cycles.
Latency problems may occur in a memory chip supporting burst read because there is only one burst state machine (BSM) employed to control the burst operations. The BSM's primary job is to provide subsequent addresses to the memory once the starting address has been given. Since there is only one BSM, it is not possible to operate in burst mode simultaneously for more than one channel.
For the reasons stated above and for additional reasons stated hereinafter, which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a multichannel pipelined burst mode non-volatile memory. The above-mentioned problems of traditional burst mode memories and other problems are addressed by the present invention, at least in part, and will be understood by reading and studying the following specification.